![]() ![]() This can be a very difficult task, and is prone to error (incorrect programming, missed cases, etc.). Tri-state conditions must be carefully coded into your STA tool in order for them to be considered. Considering that tri-state is not usually assumed in timing analysis, this is the most likely source of the timing discrepancy. The other potential issue is bus1 starts in a high impedance state ( ZZZZZZZZ). However, this problem manifests itself in later cycles after all registers have been initialized. This could cause the simulator to give weird answers until all registers are loaded or reset. In logic simulations, U implies that the line is either a 1 or 0, but a register driving it was not initialized properly. Immediately, the UUUUUUUU on bus3 looks very suspicious, and is a possible issue with initialization. Without any serious setup of STA, some common assumptions are that all inputs are valid by the time the clock rises, and that all states are known (meaning a logic 1 or 0). Since you have a problem, this means that the scenarios that static timing analysis (STA) is checking are not covering the actual usage of your circuit. ![]() Looking through your timing report, there is nothing that indicates a potential issue.
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